1. Technical Field
The present invention relates to amplitude limiting amplifier circuits and more particularly to improvements in amplitude limiting amplifier circuits for amplifying such kinds of sensor signals for use in VTRs and video movies as frequency signals (FG) for indicating rotational speeds of drums and capstans, and control signals (CTL) to be read from magnetic tapes.
2. Background Art
A conventional amplitude limiting amplifier circuit of the sort described above comprises an amplifier and an amplitude limiting circuit. FIG. 5 shows an example of the amplitude limiting amplifier circuit. An operational amplifier 1 in FIG. 5 is an inverted amplifier in which bias voltage VB is applied to a non-inverted input terminal 2, whereas a signal to be amplified is input to an inverted input terminal 3 via a capacitor 4 and a resistor R.sub.2 which are used for cutting direct current. A feedback resistor R.sub.1 is connected between an output terminal 5 and the inverted input terminal 3. An amplitude limiting circuit 6 has a pair of parallel diodes 7, 8 and is connected to the feedback resistor R.sub.1. The diode 7 is connected in the direction in which forward current flows from the inverted input terminal 3 to the output terminal 5, whereas the diode 8 is connected in the opposite direction.
With the arrangement above, the voltage of the output terminal 5 varies in such a way as to center around the bias voltage VB when the input signal is amplified by the operational amplifier 1. The forward current flows through the diode 7 when the voltage of the output terminal 5 becomes higher than that of the inverted input terminal 3, thus causing the potential difference to reach the forward voltage drop Vf of the diode. The maximum voltage value of the output terminal 5 is thus limited to VB+Vf. On the other hand, the forward current flows through the diode 8 when the voltage of the output terminal 5 becomes lower than that of the inverted input terminal 3, thus causing the potential difference to reach Vf. The minimum voltage value of the output terminal 5 is thus limited to VB-Vf. Therefore, the signal output from the output terminal 5 is what has amplitude Vf centering around the bias voltage VB.
However, the following problems are posed when a CMOS integrated circuit is used to form the conventional amplitude limiting amplifier circuit. Although the diodes 7, 8 are required to be independent of other peripheral circuits, they can hardly be kept afloat in ordinary CMOS processing. In order to make the diodes 7, 8 afloat in such CMOS processing, insulating films or insulating layers will have to be formed to provide a multilayer construction and this attempt may otherwise result in not only lowering the integration ratio of the circuit but also complicating the process of manufacture.
FIG. 6 shows another example of the conventional amplitude limiting amplifier circuit. An amplitude limiting circuit 9 in this circuit has a pair of P-channel MOSFETs 10, 11 The drain terminal of the P-channel MOSFET (hereinafter called "PMOS") 10 and the source terminal of PMOS 11 are connected to the inverted input terminal 3 of an operational amplifier 1, whereas the source terminal of the PMOS 10 and the drain terminal of the PMOS 11 are connected to the output terminal 5 of the operational amplifier 1. Moreover, the gate terminal of the PMOS 10 is connected to the inverted input terminal 3, whereas the gate terminal of the PMOS 11 is connected to the output terminal 5.
The voltage of the output terminal 5 varies in such a way as to center around bias voltage VB in response to an input signal in that case as well. In other words, current flows from the source to drain of the PMOS 10 when the voltage of the output terminal 5 becomes higher than that of the inverted input terminal 3, thus causing the potential difference to reach the threshold level Vth.sub.1 of the PMOS 10. The maximum voltage value of the output terminal 5 is consequently limited to VB+Vth.sub.1. On the other hand, the current flows from the source to drain of the PMOS 11 when the voltage of the output terminal 5 becomes lower than that of the inverted input terminal 3, thus causing the potential difference to reach the threshold level Vth.sub.2 of the PMOS 10. The minimum voltage value of the output terminal 5 is consequently limited to VB+Vth.sub.2.
However, the back gate voltages of the PMOSs 10, 11 are both locked to power supply voltage V.sub.DD. The source-to-drain potential difference (=threshold level Vth.sub.1) resulting from the flow of the current from the source to drain of the PMOS 10 when the voltage of the output terminal 5 becomes higher than the voltage VB of the inverted input terminal 3 in the circuit above differs from the source-to-drain potential difference (=threshold level Vth.sub.2) resulting from the flow of the current from the source to drain of the PMOS 11 when the voltage of the output terminal 5 becomes lower than the voltage VB of the inverted input terminal 3. The threshold levels Vth.sub.1, Vth.sub.2 thus differ from each other. This amplitude limiting amplifier circuit is incapable of amplifying the input signal in such a way as to limit the amplitude evenly in the vertical direction (=output level direction). The PMOSs 10, 11 may be replaced with respective N-channel MOSFETs (hereinafter called "NMOS"); however, the back gate voltages of both are locked to GND (0[V]) in this case. For this reason, the threshold levels Vth.sub.1, Vth.sub.2 still remain uneven and therefore the amplitude cannot also be limited evenly in the vertical direction.